Repeat Problem 12-1 for the following sequence of read addresses: 0, 4, 12, 8, 14, 1C, 1A, 28, 26, 2E, 36, 30, 3E 38, 46, 40, 4E, 48, 56, 50, 5E, 58.

Problem 12-1

A CPU produces the following sequence of read addresses in hexadecimal:
54, 58, 104, 5C, 108, 60, F0, 64, 54, 58, 10C, 5C, 110, 60, F0, 64.
Supposing that the cache is empty to begin with, and assuming an LRU replacement, determine whether each address produces a hit or a miss for each of the following caches:

(a) direct mapped in Figure 12-3.

(b) fully associative in Figure 12-4.

(c) two-way set associative in Figure 12-6.

Figure 12-3

Figure 12-4

Figure 12-6

Transcribed Image Text:

9 8 7 6 5 4 3 2 Tag Index Index 000 001 010 011 100 101 110 111 (a) Memory address Tag Data 00000 Cache 1 0 Byte Address 0000000000 0000000100 0000001000 0000001100 0000010000 0000010100 0000011000 0000011100 1111100000 1111100100 1111101000 1111101100 1111110000 1111110100 1111111000 1111111100 Data ... Main memory (b) Cache mapping