Consider an instruction sequence used for a memory-to-memory copy. 1w $t2,100 ($t5) sw t2,200 ($t6) The value in $t2 to be stored into memory by the sw is actually not needed until MEM stage of the MIPS pipeline. Below is a drawing showing the two instructions being pipelined. Modify this figure in a manner similar to Figure 4.29 on page 279 of your text to show how the value could be forwarded to avoid a stall. EX MEM sw S12,100(S15) EX MEM Rewrite the following stall formula so this code sequence won't stall. (25 points) if (ID/EX.MemRead AND (ID/EX.RegisterRtIF/ID.RegisterRs OR ID/EX.RegisterRt-IF/ID.RegisterRt) AND ID/EX.RegisterRt !- 0) stall the pipeline Consider an instruction sequence used for a memory-to-memory copy. 1w $t2,100 ($t5) sw t2,200 ($t6) The value in $t2 to be stored into memory by the sw is actually not needed until MEM stage of the MIPS pipeline. Below is a drawing showing the two instructions being pipelined. Modify this figure in a manner similar to Figure 4.29 on page 279 of your text to show how the value could be forwarded to avoid a stall. EX MEM sw S12,100(S15) EX MEM Rewrite the following stall formula so this code sequence won't stall. (25 points) if (ID/EX.MemRead AND (ID/EX.RegisterRtIF/ID.RegisterRs OR ID/EX.RegisterRt-IF/ID.RegisterRt) AND ID/EX.RegisterRt !- 0) stall the pipeline