Consider an instruction sequence used for a memory-to-memory copy.

lw $t2,100($t5)

sw $t2,200($t6)

The value in $t2 to be stored into memory by the sw is actually not needed until MEM stage of the MIPS pipeline. Below is a drawing showing the two instructions being pipelined. Modify this figure in a manner similar to Figure 4.29 on page 279 of your text to show how the value could be forwarded to avoid a stall.

Rewrite the following stall formula so this code sequence wont stall

if (ID/EX.MemRead AND

(ID/EX.RegisterRt == IF/ID.RegisterRs OR

ID/EX.RegisterRt == IF/ID.RegisterRt) AND I

D/EX.RegisterRt != 0)

stall the pipeline

EX WB EX MEM IF sw St2,100(St5) EX WB EX MEM IF sw St2,100(St5)