Consider an nMOS transistor charging a capacitor C. At t = 0, Voltage at X is...
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Consider an nMOS transistor charging a capacitor C. At t = 0, Voltage at X is 0 and a logic high voltage VH > VTn is applied to terminals A and Inl. This results in the capacitor charging through the nMOS transistor. Use the simple MOS transistor model with ideal saturation. In1 F a) Derive an expression for the voltage at node X as a function of time in terms of transistor parameters and applied voltages. b) You are given that VH = 1.7V, VTn = 0.4V and the voltage at X reaches 0.5V at t = 100ps. i) What will be the voltage at X at t = 200ps? ii) At what time will the voltage at node X reach 1.2V? Consider an nMOS transistor charging a capacitor C. At t = 0, Voltage at X is 0 and a logic high voltage VH > VTn is applied to terminals A and Inl. This results in the capacitor charging through the nMOS transistor. Use the simple MOS transistor model with ideal saturation. In1 F a) Derive an expression for the voltage at node X as a function of time in terms of transistor parameters and applied voltages. b) You are given that VH = 1.7V, VTn = 0.4V and the voltage at X reaches 0.5V at t = 100ps. i) What will be the voltage at X at t = 200ps? ii) At what time will the voltage at node X reach 1.2V?
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Related Book For
Analysis and Design of Analog Integrated Circuits
ISBN: 978-0470245996
5th edition
Authors: Paul R. Gray, ? Paul J. Hurst Stephen H. Lewis, ? Robert G. Meyer
Posted Date:
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