A differential circuit employing active loads is shown in Fig. 7.42. Bias voltage V B is adjusted

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A differential circuit employing active loads is shown in Fig. 7.42. Bias voltage VBis adjusted so that the collectors of Q1and Q2are at +5 V dc. Biasing resistors are RB1= 10 kΩ and RB2= 20 kΩ. Calculate the low-frequency, small-signal voltage gain Ï…o/Ï…i, and use the zero-value time-constant method in the DM half-circuit to estimate the ˆ’3-dB frequency of the DM gain. Use the device data in Problem 7.25.

Data from Prob. 7.25:

Data: npn: β = 100, fT = 500 MHz at IC = 1 mA, Cμ0 = 0.7 pF, Cje = 3 pF (at the bias point), Ccs0 = 2 pF, rb = 0, and VA = 120 V. Assume n = 0.5 and ψ0 = 0.55 V for all junctions. pnp: β = 50, fT = 4 MHz at IC = ˆ’0.5 mA, Cμ0 = 1.0 pF, Cje = 3 pF (at the bias point), Cbs0 = 2 pF, rb = 0, and |VA| = 50 V. Assume n = 0.5 and ψ0 = 0.55 V for all junctions.

Fig. 7.42:

+10 V VR Q4 o Vo 20 k2 20 k2 O2 w- Rg2 O5 RB1 -10 V

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Analysis and Design of Analog Integrated Circuits

ISBN: 978-0470245996

5th edition

Authors: Paul R. Gray, ‎ Paul J. Hurst Stephen H. Lewis, ‎ Robert G. Meyer

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