Consider repeating load $($lw$)$ data from the following addresses using MIPS processer with $32$ bits address.

Mem $[0$x$10010040]$

Mem $[0$x$10010044]$

Mem $[0$x$10010090]$

Mem $[0$x$10010094]$

If the loading was repeated for only twice, what are the Miss rates of using direct mapped with $8$ sets, block size $=1$ word; $2-$way set associative cache with $4$ sets, block size $=1$ word and direct mapped cache with $4$ sets, block size $=2$ words?

Please provide details of analysis,

Cache Type DMC b$=12-$way b$=1$ DMC b$=2$

Miss Rate $.....................................$