$3.$ Consider repeating load $("$lw$")$ data from the following addresses using MIPS processer with $32$ bits address.

Mem$[0$x$10010040]$

Mem$[0$x$10010044]$

Mem$[0$x$10010090]$

Mem$[0$x$10010094]$

If the loading was repeated for only twice, what are the Miss rates of using direct mapped with $8$ sets, block size $\backslash (=1\backslash )$ word; $2-$way set associative cache with $4$ sets, block size $\backslash (=1\backslash )$ word and direct mapped cache with $4$ sets, block size $\backslash (=2\backslash )$ words?

Please provide details of analysis, simply filling the table gets $0$ point.