Consider the design of a processor, with a max instruction length of 600 ps. The propagation delay to load a register is 25 ps

What is the minimum clock cycle time, the instruction latency and CPU throughput using serial execution?

What is the minimum clock cycle time, the instruction latency and CPU throughput using a pipelined execution with 8 equal stages?

Consider a design which used n equal stages. What is the minimum clock cycle time, the instruction latency and CPU throughput expressed as a function of n? (You may wish to check that your generalization agrees with your results from parts (a) and (b), i.e., by substituting n = 1, 8.)