Consider the following C code segment

 z = 1.0; if ( x != 0 ) { 

z = c*x + y; }

The C code segment can be translated to the following sequence of RISC-V instructions. Note: register x0 always contains zero.

LD

ADDI

BEQ

LD

MUL

ADD

DONE: SD

x4, 16(x2) x6, x0,1 x4, x0, DONE x12, 22(x6) x10, x4, x8 x6, x10, x12 x6, 0(x3) 

/* Load x */ /* set z=1 */ /* if x==0 goto DONE */ /* Load y */ /* Calculate c * x */ /* Add c*x + y */ /* Store z */ 

/*assume c is in register x8*/ 

(a) Find all dependencies in the code segment and list them by category (i. e., data dependence, output dependence, anti-dependence and control dependencies). Your list should show the register, source instruction, and destination instruction.

(b) Show the timing diagram of this sequence of instructions using a pipelining timing chart. What are the number of cycles it takes, and the number of stall cycles, assuming the following?

Regular 5-stage pipeline without forwarding or bypassing hardware. The pipeline stages are IF, ID, EX, MEM, and WB.

Register read and write can be done in the same clock cycle based on forwards through the register file.

Dual-port memory, memory references take 1 cycle.

No branch prediction.

No special hardware to speed up branch operations, i.e. the outcome of a branch is

known after the WB stage of that instruction.

(c) (8 points) How many cycles does this code sequence take assuming that the branch in the C code is handled by predicting it is not being taken (i.e., x = 0, branch is taken in the assembly code).

(d) How many cycles does this code sequence take assuming the 5-stage RISC pipeline with full forwarding and bypassing hardware, and that the branch in the C code is handled by predicting it is not being taken (i.e., x = 0, branch is taken in the assembly code). Note: Branch outcomes and targets are known now at the end of ID stage.

(e) In order to reduce the branch penalty, we would like to apply a delayed branch approach. Please indicate which instruction could be used to fill the delayed branch slot.

(f) Explain what is the forwarding technique and what problem does it solve? Give examples based on the RISC-V 5-stage pipeline design.