Consider the following circuit and specifications:

Typical hold time $=1\mathrm{.}8$ns

Typical clock frequency $=50$MHz

Typical setup time $=1\mathrm{.}5$ns

Consider a positive clock skew: t$\_$skew $=0\mathrm{.}4$ ns$.$ From the options below, find the maximum possible

hold time $($t$\_$hold$)$ of the flip$-$flops that would have no hold violation for the above design?

$1\mathrm{.}8$ ns

$2\mathrm{.}5$ns

$3$ns

$2$ns

All of these will have hold violations

$($The selected answer of $3$ns from the images was proven to be incorrect$).$