Question: Consider the following code: module FF (Q, X, Clk, rst); output Q: input X, Clk, rst; reg Q: always @ (negedge CLK, negedge rst) if

Consider the following code: module FF (Q, X, Clk, rst); output

Consider the following code: module FF (Q, X, Clk, rst); output Q: input X, Clk, rst; reg Q: always @ (negedge CLK, negedge rst) if (rst == 0) Q

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