Question: You are given the following Verilog code: module leprechaun ( input logic CLK , RST , output logic [ 3 : 0 ] Q )

You are given the following Verilog code:
module leprechaun ( input logic CLK, RST, output logic [3:0] Q ); logic [3:0] next_Q; always_ff @(posedge CLK) if (RST) Q <=4b0010; else Q <= next_Q; always_comb begin next_Q[0]= ~Q[0]; next_Q[1]= Q[1]^ Q[0]; next_Q[2]= Q[2]^ &Q[1:0]; next_Q[3]= Q[3]^ &Q[2:0]; end endmodule
When the value of Q is 4b1001, what will Q be after three rising edges of clk while RST is 0?
Question 17 options:
4'b1001
4'b1101
None of the others
4'b0101
4'b1011

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