Question: Consider the following code sequence. Assume Direct mapped cache. STR R 3 , 2 5 6 ( R 0 ) LDR R 1 , 2

Consider the following code sequence. Assume Direct mapped cache.
STR R3,256(R0)
LDR R1,2048( R0)
LDR R2,256(R0)
Write-through cache maps 256 and 2048 to the same block. A four words write
buffer is not checked on a read miss. Will the value in register R2 always be equal
to the value in register R3 or R2? Discuss.

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