Consider the following code sequence (below) executing on CPU implementing Tomasulo's algorithm with Reorder Buffer. Assume the following 1. The architecture has one FP adder/subtractor, One FP Multiplier, Two integer addition units (for integer addition operations and memory address calculation). 2. You have two reservation stations for each functional unit. 3. Assume the following: execution of the Mul instruction requires 6 clock cycles while Add/SUB requires and Sub 3 requires clock cydes. All integer units requires 1 clock cycle. Read/Write on memory takes 3 cycle 4. Assume that only one CDB is available. Fill the following table (next page) entering the clock cycle when the instructions issue, execute (from- to), write to CDB, and commit. Instruction Issue EX End WB Commi Commit Begin Addi FO, FO, 8 L.D F1, 0[FO) L.D F2, 4(FO) Add F4, F2, F12 Mul F5, F4, F1 Add F6, F2, F3 Sub F8, F2, F5 S.D F8, 0(F10) Consider the following code sequence (below) executing on CPU implementing Tomasulo's algorithm with Reorder Buffer. Assume the following 1. The architecture has one FP adder/subtractor, One FP Multiplier, Two integer addition units (for integer addition operations and memory address calculation). 2. You have two reservation stations for each functional unit. 3. Assume the following: execution of the Mul instruction requires 6 clock cycles while Add/SUB requires and Sub 3 requires clock cydes. All integer units requires 1 clock cycle. Read/Write on memory takes 3 cycle 4. Assume that only one CDB is available. Fill the following table (next page) entering the clock cycle when the instructions issue, execute (from- to), write to CDB, and commit. Instruction Issue EX End WB Commi Commit Begin Addi FO, FO, 8 L.D F1, 0[FO) L.D F2, 4(FO) Add F4, F2, F12 Mul F5, F4, F1 Add F6, F2, F3 Sub F8, F2, F5 S.D F8, 0(F10)