Question: Consider the following instructions executed on a computer that has a five-stage pipeline Load R1, 0(RO) Load R2, 4(RO) Add R3, R1, R2 Store

Consider the following instructions executed on a computer that has a five-stage

Consider the following instructions executed on a computer that has a five-stage pipeline Load R1, 0(RO) Load R2, 4(RO) Add R3, R1, R2 Store R3, 8(RO) 1) How many memory access operations occur when these instructions are fetched to the processor and executed? 2) Assume all memory access operations are cache hit, which can be completed in one cycle. How many cycles does it take to execute all the instructions if data forwarding is allowed?

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