Consider the following sequence of instructions executed on the basic 5 stage pipeline... add $t3, $t2, $t1 or $t5, $t3, $t4 and i $t6, $t7, $t4 add $t7, $t2, $t1 a) Assuming our processor has no forwarding or hazard detection, insert a minimal amount of pipeline stalls to ensure correct execution (you may stall the pipeline with the instruction add $zero, $zero, $zero). b) Assuming our processor has no forwarding or hazard detection, rearrange the instructions and add stalls only if necessary to ensure proper execution. The values contained in the registers after executing your modified code should be equivalent to the unmodified execution