Consider the following VHDL code and identify the syntax error$($s$)$ within it:

Select one:

a$.$ The use of else at the end of the when$-$else construct is incorrect.

b$.$ The BIT$\_$VECTOR literals for comparison with SELECTOR are improperly formatted.

c$.$ There is an improper use of the BIT type in the conditions.

d$.$ A concluding else condition is required for the when$-$else construct.