Consider the multi-cycle and single-cycle datapath from lecture but with the delays shown for each operation. (L11) Read memory Write memory Read register file Write register file ALU All other operations 10 ns 15 ns 3 ns 6 ns 6 ns 0 ns (a) What is the clock period for the single-cycle processor if we only had to support add, nor, beq and sw? [4] (b) What is the clock period for the single-cycle processor if we support all LC2K instructions except jalr? [4] (c) If we can decrease the delay for one of the operations by 10%, which operation should it be for our single-cycle datapath which supports all LC2K instructions except jalr? What is the clock period after improvement? [7] (d) If we can decrease the delay for one of the operations by 10%, which operation should it be for our multi-cycle datapath which supports all LC2K instructions except jalr? What is the clock period after improvement? [7]