Goal: Create the datapath and control logic for a $6-$instruction CPU. Run your CPU with a

self$-$checking testbench $($testbench$.$sv$)$ with vectors from "Dmem$\_$expected.tv$"$ and executes

the first $5$ numbers in the Fibonacci sequence.

Here are the details about the $6$ instructions:

Each instruction contains a $3-$bit Opcode and the binary code for one of $3$ instruction types:

Load: LD Ra$,$ a$-$specifies the operation RF$[$Ra$]=$ D$[$a$].$ A move from the data

memory specified by a$5$ a$4$ a$3$ a$2$ a$1$ a$0$ into the register$-$file register whose location

is specified by the bits Ra$2$ Ra$1$ Ra$0.$ The binary machine code for the Load instruction

is

Ob$000$ Ra$2$ Ra$1$ Ra$0$ a$5$ a$4$ a$3$ a$2$ a$1$ a$0$

Store:ST a$,$ Rc$-$specifies the operation D$[$a$]=$RF$[$Rc$].$ A move of data in the

opposite direction as the Load instruction: From the Register$-$file location Rc$2$ Rc$1$ Rc$0$

to data memory location a$5$ a$4$ a$3$ a$2$ a$1$ a$0.$ The binary machine code for the Store

instruction is

Ob$001$ a$5$ a$4$ a$3$ a$2$ a$1$ a$0$ Rc$2$ Rc$1$ Rc$0$

where the function is performed on the data in Rb $2$ Rb $1$ Rb $0$ and Rc $2$ Rc $1$ Rc $0.$

result is stored the register specified by Ra $2$ Ra $1$ Ra $0.$ The functions in XXX are AD

SUB, AND and OR:

ADD Ob$010$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

SUB Ob$011$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

AND Ob$100$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

OR Ob$101$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

The datapath will have a Proaram Counter. Instruction Memory. Data Memory. Reaister File.

ALU$-$type: xxXRa,Rb$,$Rc$-$Specifies the operation RF$[$Ra$]=$F$($RF$[$Rb$],$RF$[$Rc$])$ where the function is performed on the data in Rb $2$ Rb $1$ Rb $0$ and Rc $2$ Rc $1$ Rc $0.$ The result is stored the register specified by Ra$2$ Ra$1$ Ra$0.$ The functions in XXX are ADD, SUB, AND and OR:

ADD Ob$010$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

SUB Ob$011$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

AND Ob$100$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

OR Ob$101$ Ra$2$ Ra$1$ Ra$0$ Rb$2$ Rb$1$ Rb$0$ Rc$2$ Rc$1$ Rc$0$

The datapath will have a Program Counter, Instruction Memory, Data Memory, Register File, $2$:$1$ muxes and ALU. In a single$-$cycle the CPU will fetch the instruction from the Instruction Memory, Read from the Memory to the Register File $($Load$),$ perform the ALU $($for ALU type instructions$)$ and write back to the Memory from the Register File $($Store$).$

The CPU microarchitecture :

Part $1-6-$instruction CPU Control Logic

In this section, we will create the control logic for the $6-$instruction programmable processor.

Based on the $3-$bit input Instruction$[11$:$9].$ Name this verilog file controller.sv

The ALUcontrol table is:

Create a testbench to test your control logic to see the outputs change for each of the following instructions: LD$,$ ST$,$ ADD, SUB, AND, OR

Include a snapshot of the EDA playground waveform showing the correct outputs for the above sequence and fill out the below table with the values in binary.

Cycle # $123456$ Instruction LD ST ADD SUB AND OR RF W$\_$we ALUcontrol DMEM we Mux$\_$select M$0$ Mux$\_$select M$1$ please help me to this testbench.sv$,$ design.sv and controller.sv please