Consider the multiplication datapath discussed in lecture. Register A and Register P are 8-bits wide. Register B is 4-bits wide. The ALU outputs O when OP is O and A +P when OP is 1. X and Y will be zero- extended to 8-bits as needed. X START Y Data inputs 0 1 SA 1 0SB >1 D A (2N-bit reg) ENTILA D B (N-bit reg) 0 EN Input Name Value Input X Ocd Input Y O.cd LB 0 B_010) =O? Register states B OP4 Control FSM ALU OP Register Name State Reg A 0x15 Reg B Ord Reg P D 0x7f| LP P (2N-bit reg) EN 0 Control signals DONE Control Signal Value Load A (LA) 0 Shift A (SA) 0 Load B (LB) 0 Shift B (SB) 1 Load P (LP) 0 ALU operation (OP) 1 Assuming that the datapath has the input data, state values stored in the registers, and control signals shown to the right, what state will be stored in the registers after the next positive clock edge? Provide your answers in hexadecimal. Add the prefix "Ox" in front of your answer. Make sure that you have the right number of bits in your final answer. Final state of regA = Ox Final state of regB = Ox Final state of regP = Consider the multiplication datapath discussed in lecture. Register A and Register P are 8-bits wide. Register B is 4-bits wide. The ALU outputs O when OP is O and A +P when OP is 1. X and Y will be zero- extended to 8-bits as needed. X START Y Data inputs 0 1 SA 1 0SB >1 D A (2N-bit reg) ENTILA D B (N-bit reg) 0 EN Input Name Value Input X Ocd Input Y O.cd LB 0 B_010) =O? Register states B OP4 Control FSM ALU OP Register Name State Reg A 0x15 Reg B Ord Reg P D 0x7f| LP P (2N-bit reg) EN 0 Control signals DONE Control Signal Value Load A (LA) 0 Shift A (SA) 0 Load B (LB) 0 Shift B (SB) 1 Load P (LP) 0 ALU operation (OP) 1 Assuming that the datapath has the input data, state values stored in the registers, and control signals shown to the right, what state will be stored in the registers after the next positive clock edge? Provide your answers in hexadecimal. Add the prefix "Ox" in front of your answer. Make sure that you have the right number of bits in your final answer. Final state of regA = Ox Final state of regB = Ox Final state of regP =