Consider the multiprocessor system shown in Figure $133.$ This system has two $32-$bit MIPS like processors, P$1$ and P$2,$ with a $5-$stage pipeline and all forwarding paths en$-$ abled $($E$->$E$,$ M$->$E and W$->$D$).$ The two processors have separate instruction memor$-$ ies from which a new instruction can be fetched every cycle, but they share the same data memory over a $256-$bit shared data bus. When a processor needs to access the shared memory it needs to have exclusive access to the shared bus. Hence, if the bus is busy, the processor stalls until it gets exclusive access to it to perform the bus trans$-$ action. Since accessing the shared memory can be a bottleneck, each processor has a private $128$KB$,$ direct$-$mapped, write$-$back data cache. The data caches can be accessed in a single cycle and each cache line holds $32$ bytes of data.