Consider the pipelined MIPS implementation shown in Figure $4\mathrm{.}51($page $316).$ The value of the

PCSrc signal is computed in the MEM stage. Could the PCSrc signal be computed in the EX stage

instead $?$ If so$,$ what would be the advantages of making this change? Also, what would be the

disadvantages of making this change? Hint: Take into account both performance and implementation

complexity considerations. Also, consider the possibility that a change may be potentially

advantageous, but the benefits actually depend on another change to also be made.