Consider the sequential circuit implementing serial addition built with two shift registers, a $1-$bit full adder and a D flip$-$flop $($Figure $6\mathrm{.}5$ in Morris Mano & Michael Ciletti, Digital Design$).$ Design and implement in Verilog a $4-$bit version of this circuit. Use the behavioral implementation behavioral$\_$serial$\_$adder.vl and make the following changes$/$additions:

$1.$ Create a logic diagram of the circuit. Use Figure $6\mathrm{.}5$ and update it using the structure of the behavioral model $($add a $2$x$1$ multiplexer and parallel inputs to the shift registers$).$

$2.$ Cleate a logic diagram of the shift register with parallel load as implemented in module shiftreg $($block level multiplexers and D$-$flip$-$flops$).$

$3.$ Create a state diagram of the serial adder.

$4.$ Implement modules shiftreg and serial$\_$adder at gate$-$level using gate$-$level D$-$flip$-$flops, full adder, and $2$x$1$ multiplexers

$5.$ Test the circuit with several inputs $($adding positive and negative numbers$)$ and show the output.

$6.$ Write a report, including the logic diagrams, the state diagram, the Verilog source code and the test results. Fig $6\mathrm{.}5$ is attached here. and behavioral$\_$serial$\_$adder.vl is below. $//4-$bit adder using shift registers and $1-$bit serial adder

$//$ Behavioural model

module adder$($x$,$y$,$S$,$Load,Clock$)$;

input $[3$:$0]$ x$,$y;

input Load,Clock;

output $[3$:$0]$ S;

wire $[3$:$0]$ PO;

shiftreg r$1($SI$,$x$,$SO$1,$S$,$Clock,Load$),$

r$2(1\text{'}$b$0,$y$,$SO$2,$PO$,$Clock,Load$)$;

serial$\_$adder sa$($SO$1,$SO$2,$SI$,$Clock,Load$)$;

$//$ Uncomment the following line to trace execution

$//$ always @$($negedge Clock$)$ $monitor$("\%$b $\%$b$",$S$,$PO$)$;

endmodule

$//$ Behavioral shift register with parallel load

$//$ Load$=1->$ load;

$//$ Load$=0->$ shift

module shiftreg $($SI$,$PI$,$SO$,$PO$,$Clock,Load$)$;

input Load,Clock;

input SI; $//$ Serial input

input $[3$:$0]$ PI; $//$ Parallel input

output SO; $//$ Serial output

output $[3$:$0]$ PO; $//$ Parallel output

reg $[3$:$0]$ R; $//$ Register

assign SO $=$ R$[0]$;

assign PO $=$ R;

always @$($negedge Clock$)$

if $($Load$)$ R $=$ PI; $//$ Parallel load

else begin $//$ Shift right

R $=$ R$>>1$;

R$[3]=$ SI;

end

endmodule

$//$ Behavioral model of $1-$bit serial adder

module serial$\_$adder$($x$,$y$,$S$,$Clock,Clear$)$;

input x$,$y$,$Clock,Clear;

output S;

reg D; $//$ simulating D flip$-$flop

wire C$1$;

assign $\{$C$,$S$\}=$ x$+$y$+$D; $//$ dataflow binary adder

assign C$1=$ Clear $?0$ : C; $//$ behavioral $2$x$1$ multiplexer

always @$($negedge Clock$)//$ load D on negative edge

D $=$ C$1$;

endmodule

module test;

reg signed $[3$:$0]$ A$,$B;

reg Load, Clock;

wire signed $[3$:$0]$ S;

adder add $($A$,$B$,$S$,$Load,Clock$)$;

always #$1$ Clock $=$ ~Clock; $//$ Generate a clock edge at every time unit

initial begin

A$=5$; B$=2$;

Load$=1$; $//$ Load inputs and clear the flip$-$flop

Clock$=1$; $//$ Start Clock

#$2$ Load$=0$; $//$ Start serial adder $($enable shifing$)$

#$8$ $display$("\%$d $+\%$d $=\%$d$",$A$,$B$,$S$)$; $//$ Show sum after $4$ negaive edges

$finish; $//$ Stop clock pulses

end

endmodule