Consider this MIPS code: loop:lw $4, 0 ($16) lw $7, 4($16) add $4, $7, $4 sw $4, 0 ($23) addi $16, $16, 8 addi $23, $23, 4 bne 16, $2, loop Unroll 3 times the MIPS code (i.e., one unrolled iteration does the work of four original iterations). Make it as efficient as you can. Show timing in the 5-stage MIPS pipeline for one unrolled iteration of the loop. Assume that the number of iterations is alwavs a multiple of four. Problem 2c (30 points): Suppose we have a static 2-issue MIPS processor, as in Fig. 4.69. Show timing for one unrolled iteration of the loop from Problem 2b, using a table similar to Fig. 4.70. You should change the order of the instructions to optimize the performance. Use these assumptions for the hardware: Unit 1 for ALU/branch instructions, Unit 2 for lw/sw If an arithmetic instruction executes in cycle 1, its result can be used in cycle 2 by a lw, sw or arith instruction its result can be used in cvcle 3 bv a branch Consider this MIPS code: loop:lw $4, 0 ($16) lw $7, 4($16) add $4, $7, $4 sw $4, 0 ($23) addi $16, $16, 8 addi $23, $23, 4 bne 16, $2, loop Unroll 3 times the MIPS code (i.e., one unrolled iteration does the work of four original iterations). Make it as efficient as you can. Show timing in the 5-stage MIPS pipeline for one unrolled iteration of the loop. Assume that the number of iterations is alwavs a multiple of four. Problem 2c (30 points): Suppose we have a static 2-issue MIPS processor, as in Fig. 4.69. Show timing for one unrolled iteration of the loop from Problem 2b, using a table similar to Fig. 4.70. You should change the order of the instructions to optimize the performance. Use these assumptions for the hardware: Unit 1 for ALU/branch instructions, Unit 2 for lw/sw If an arithmetic instruction executes in cycle 1, its result can be used in cycle 2 by a lw, sw or arith instruction its result can be used in cvcle 3 bv a branch