Question: Consider two designs D 1 and D 2 for a synchronous pipelined processor. D 1 has 5 stages having 3 , 2 , 4 ,

Consider two designs D1 and D2 for a synchronous pipelined processor. D1 has 5 stages having 3,2,4,2,3 ns delay. D2 has 8 stages having an equal delay of 3 ns. Which design is better and how much time can be saved by it for executing 500 instructions

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