Course Assignment

$($#$1)$ Combinational Circuit design, synthesis and simulation

For the XOR gate shown,

Code for $3$ levels of the design: Gate, RTL$,$ and Behavior Levels. Submit $($screenshot and source file in ${?}^{**}.$txt$)$ the designs after proven working

Code one single Test Bench $($TB$).$ Submit $($screenshot and source file in $*{?}^{txt}$ the TB after proven working

Then, use the IDE tool,

edaplayground.com, to run synthesis and simulation. Submit screenshots of synthesized circuit an simulation waveform of one design and its TB$.$

$\backslash$table$[[A,B,Y=$A XOR B$],[0,0,0],[0,1,1],[1,0,1],[1,1,0]]$