Course:(( computer architecture)) Problem1: True/False:

1- In Booths algorithm, a Q of 110011 requires one Add and one Subtract operations.

2 -In Decode Instruction phase, the CPU decodes the content of the Data Register (DR) to find out the type of operation to be executed.

3 -In x86, interrupt number 8 has CS:IP value stored at location CS*16 + IP.

4- Cache hit ratio always increases when cache size increases.

5 -ASR operation on 0110 results in 0011

6 -CISC machines provide more instructions than RISC machines.

7 -SDRAM is a DRAM with small Static RAM module built inside of it.

8 -The number of address lines for a 256K x 16 memory organization is 16.

9 -A cache dirty-bit is needed for a cache write back policy NOT for write through.

10- AR is a special register used to store the address of next instruction to be fetched.