Course: ((computer architecture)) Problem1: True/False.

11 -EPROM is a ROM that is electrically Erasable and Programmable device.

12 -Parity is a way to detect and correct single errors on a data bus.

13 - T: R1 <--- R2 + R3; stores the outcome of (R2 OR R3) in R1 when T is true.

14 -A direct mapped cache of 16 lines and a tag field of 2 bits hints that the main memory is divided into 64 blocks.

15 - A DRAM consists of cells that are smaller but faster than SRAM cells.

16- Execution time is a better performance measure than MIPS.

17 - An instruction format with 5 bits OpCode field, and an additional direct/indirect bit requires the CPU to execute up to 64 different operations.

18 - RAID storage systems typically consist of an array of magnetic tapes.

19 - In a six-stage pipeline arch, it takes 10 CPU cycles to execute 5 back to back instructions.

20- In an n-way set associative cache, n is always a power of 2.