Course: ECEN 3734 - Computer Design

Topic: VHDL Code

Question: For the given VHDL code:

(a) Describe the function of the VHDL codes and develop force statement to verify the output of Z.

(b) Draw the timing diagram of the circuit based on force commands in part (a).

Problem 2 (30 pt.): For the following VHDL codes. LIBRARY ieee USE ieee.std_iogic_1164.all i USE ieee.std_iogic_signed.all ENTIIY prob2 IS PORT N, D, Q, Resetn, Coin : IN STD LOGIC i OUT STD_LOGIC END prob2: ARCHITECTURE Behavior OF prob2 Is SIGNAL X: STD LOGIC_VECTOR (4 DOWNTO 0) SIGNAL S STD LOGIC_VECTOR (5 DOWNTO 0) BEGIN x(0)