CPU $1($pipelined$)$:

$6-$stage pipeline $($Instruction Fetch, Decode, Execute, Memory, Write Back, Flush$).$

Each stage takes $4$ ns$.$

Due to data hazards, there is a pipeline delay of $4$ ns after every $5$ instructions.

CPU$2($pipelined$)$:

$4-$stage pipeline $($Memory$,$ Instruction Fetch, Decode$/$Execute$,$ Write Back$).$

Each stage takes $5$ ns$.$

Due to data hazards, there is a stall $($pipeline delay$)$ of $2$ ns after every $10$ instructions.

CPU $($non$-$pipelined$)$:

Executes each instruction in $5$ ns$.$

$1)$ Calculate the effective throughput of CPU $1,$ considering the pipeline delay due to data hazards.

$2)$ Compare throughput of CPU$1$ with the throughput of the non$-$pipelined CPU.

$3)$ Which CPU would be more efficient for a program with a high frequency of data hazards, explain your answer.

$4)$ Compute the total execution times for each instruction for each CPU.

Please explain the calculations and reasoning like im $5.$