Question: create a 1 bit adder/subtractor in structural verilog with a test bench. Create a truth table for each output-bit in this bit-slice module, as a

create a 1 bit adder/subtractor in structural verilog with a test bench.

Create a truth table for each output-bit in this bit-slice module, as a function of the three input bits. Then derive the two-level SOP expressions for each output bit from your truth-tables.

Synthesize these switching expressions in structural verilog using the AND/OR/NOT gates.

Also verify that si = ai ri ci1 and carry out = ci = airi +rici1 +aici1 = majority(ai,ri,ci1)

input bit 1 = ai

input bit 2=ri =thei-thbitofB(ifT =0);orthei-thbitoftheTwos-complementofBwhenT =1 ; and input bit 3 =ci1 = the carry in from the previous bit position (i 1)

The full adder generates two output bits: output bit 1 = si = the i-th sum-bit of the result, and output bit 2 = ci = a carry out into the next-bit-position (i + 1)

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