Create a new project for an $8-$bit full$-$adder by $1)$ instantiate $1-$bit full$-$adder $8$ times and $2)$ performs $8-$bit addition directly. Synthesize the designs again and retrieve from the analysis & synthesis report the Combinational ALUT usage for logic to map the $8-$bit full$-$adders to the FPGA. Compare and comments on the results. Create your own test$-$bench to verify the functional correctness using ModelSim. You need to submit your RTL code for the $8-$bit full adder, its test$-$bench and simulation results with justification on the functional correctness of the adder.