Create a Verilog module named "grey

$\_$

code" which outputs all

$1$

$6$

$$min

$-$

terms of

$4$

$$bit grey code, given all

$1$

$6$

$$min

$-$

terms of normal binary code as input. Input Signals: A

$,$

B

$,$

C

$,$

D; Output Signal: F

$-$

$4$

$$bits

$-$

$$Index zero should be the LSB of

$"$

F

$\text{'}$

s

$"$

$$grey code output.