Question: Create a Verilog module that implements an 8-bit 2s complement up/down counter with a synchronous reset to zero and a special feature: It should not

Create a Verilog module that implements an 8-bit 2s complement up/down counter with a synchronous reset to zero and a special feature: It should not overflow. If its counting up and it hits the max positive, it should stay at that count and not roll over into a negative number. Similarly when counting down, if it hits the max negative, it should stay at that value.

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