Create, using just DMux chips as internal, the chip DMux4 with this style 1 pin layout, where the nice names 1, S1, and So correspond, in order, to in[0], in[1], and in [2], and A, B, C, and D corresond, in order, to out [0], out [1], out [2], and out [3]. B DMux4 D s1 SO and this behavior: S S. 4 B D 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 I where we are abbreviating the truth table by using I as the output, meaning for each set of values of So and S1, one of the four outputs is the same as I, while the others are 0