Data valA valE Execute Decode PC Fetch igure 441 Hardware structure of PIPE, an initial pipelined implemen inserting pipeline registers into are several shortcomings of this version that we SEQ+(Figure 4.40), we create a will deal with shortly 1. Pipelined Datapath and Control (12 points) Consider the following set of instructions mrmovq 0(%r12), %r9 nrmovq 4(%r12), %r10 irmovq $4, %r8 xorq %r13,%r14 subq %r10,%r9 rnmovqZr9, -4(%r12) (a) (9 points) Refer to Figure 4.41 in the textbook and fll in the values at cycle 5, for each pipeline (sub)register indicated below. Assume that the Fetch stage of the first instruction (mrmovq) executes in cycle 1 and assume that its address in instruction memory is 0x0004. Before execution begins, each register's value is the same as its register number (e.g. r8 is 8, r9 is 9). The value in memory is the same as the address plus 100 (e.g. address 60 holds the value 160) Dcode | Difun D.rb alC E ico EifunE.valA E.valB (b) (3 points) What are the control signals consumed (that are currently used) in cycle 5 of execution? instr valid ALUfun eCnd m Cn write Data valA valE Execute Decode PC Fetch igure 441 Hardware structure of PIPE, an initial pipelined implemen inserting pipeline registers into are several shortcomings of this version that we SEQ+(Figure 4.40), we create a will deal with shortly 1. Pipelined Datapath and Control (12 points) Consider the following set of instructions mrmovq 0(%r12), %r9 nrmovq 4(%r12), %r10 irmovq $4, %r8 xorq %r13,%r14 subq %r10,%r9 rnmovqZr9, -4(%r12) (a) (9 points) Refer to Figure 4.41 in the textbook and fll in the values at cycle 5, for each pipeline (sub)register indicated below. Assume that the Fetch stage of the first instruction (mrmovq) executes in cycle 1 and assume that its address in instruction memory is 0x0004. Before execution begins, each register's value is the same as its register number (e.g. r8 is 8, r9 is 9). The value in memory is the same as the address plus 100 (e.g. address 60 holds the value 160) Dcode | Difun D.rb alC E ico EifunE.valA E.valB (b) (3 points) What are the control signals consumed (that are currently used) in cycle 5 of execution? instr valid ALUfun eCnd m Cn write