Question: Deisgn source code: ` timescale 1 ns / 1 ps / * / / / / / / / / / / / / /
Deisgn source code:
timescale ns ps
Display module displays a BCD number to segment display
this module will always light the rightmost display on
the BASYS board.
module displayA B C D a b c d e f g dp enable;
input A B C D; bit BCD Number ABCD
output a b c d e f g dp; segment control and decimal point ACTIVE LOW
output : enable; enable for display digits
assign enable b; Always enable the least significant display digit ACTIVE LOW
assign dp ; Always turn off decimal point ACTIVE LOW
Circuits for each segment
invert inputs
not A A
B B
C C
D D;
Segment a
and AC A C
ABD AB D
BCDBCD
ABCABC;
nor a ACABDBCDABC; Use NOR for ACTIVE LOW output
Segment b Insert your design here for segment b reuse gates wherever possible
and ABAB
ACDAC D
ACDACD
ABCABC;
nor b ABACDACD ABC; already have CD
Segment c
and AB A B
AD A D
BCDBCD
ABCABC;
nor c ABADBCDABC;
Segment d
Segment e
Segment f
Segment g Insert your design here for segment g reuse gates wherever possible
endmodule
Simulation code:
timescale ns ps
Display module displays a BCD number to segment display
this module will always light the rightmost display on
the BASYS board.
module displayA B C D a b c d e f g dp enable;
input A B C D; bit BCD Number ABCD
output a b c d e f g dp; segment control and decimal point ACTIVE LOW
output : enable; enable for display digits
assign enable b; Always enable the least significant display digit ACTIVE LOW
assign dp ; Always turn off decimal point ACTIVE LOW
Circuits for each segment
invert inputs
not A A
B B
C C
D D;
Segment a
and AC A C
ABD AB D
BCDBCD
ABCABC;
nor a ACABDBCDABC; Use NOR for ACTIVE LOW output
Segment b Insert your design here for segment b reuse gates wherever possible
and ABAB
ACDAC D
ACDACD
ABCABC;
nor b ABACDACD ABC; already have CD
Segment c
and AB A B
AD A D
BCDBCD
ABCABC;
nor c ABADBCDABC
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