Question: timescale i ns / 1 ps module TEST_gate; reg(1:0)a,b; initial begin a=2'b00: #10 b=2'bll; #10 a=2'bll; end initial begin b-2'b00: #40 a-2'b01; end initial #60

timescale i ns / 1 ps module TEST_gate; reg(1:0)a,b; initial begin

timescale i ns / 1 ps module TEST_gate; reg(1:0)a,b; initial begin a=2'b00: #10 b=2'bll; #10 a=2'bll; end initial begin b-2'b00: #40 a-2'b01; end initial #60 Sfinish; endmodule Which of the following correctly represents the values of "a" and "b" at the 40th nanosecond according to the above verilog code

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