Derive equations for generating parity bits of a Hamming code generator with 6 data bits and odd parity. 3. 2. Complete the following before coming to the lab: (1) (a) Draw a block diagram showing only input and output ports for the above Hamming Code generator in your notebook. (b) Complete the following table column 2 for the listed inputs. Input (Data Bits) Output (Hamming Code) FPGA Results 1 1 1 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 3. 3. Write VHDL code for the above design. 3. 4. Write a test bench for the above design and verify it by simulation. (0.5) 3. 5. Implement in FPGA and show your board with correct tests to your tutor.