Design a $16$ bit IR $($Instruction Register$)$ with a synchronous RST$,$ where leftmost $4$ bits are used as an Output called OPCODE.

Meanwhile next $3$ fields are outputs for $34-$bit operands REG$1,$ REG$2,$ REG$3.$

Also generate another output called SPECIAL if the OPCODE is between $0$ and $3($inclusive$)$ decimal