Design a $3$ bit binary gray code counter reflective about the least significant bit.

a$)$ Draw the state transition diagram.

b$)$ Write the state transition table.

c$)$ Write the Karnaugh maps for D$-$flip flop design.

d$)$ Write and simplify the Karnaugh maps for the J $-$ K flip flop design.

e$)$ Draw the logic circuit.