Design a $3-$bit synchronous counter using toggle cells $($T flip$-$flops$)$ with as small a delay as possible between the count enable input and the $T$ input of each toggle cell.

Figure $6.$ Toggle Cell $($T Flip$-$flop$)$

$10.$ Modify the $3-$bit synchronous counter design of Problem $9$ so that it has a synchronous clear. The preset and clear of a standard toggle cell are asynchronous not synchronous so the design should "clear" the cells via the T inputs of the cells.