Design a 3-bit register using D-FFs. Design a 3-bit counter with the following count sequence: 0, 7, 3, 1, 5, 2, 0, 7, 3, 1, NOTE .Use ABC to label bits in the count, where A is the MSB, and C is the LSB. Use A B and C to designate the bits in the next count. Use don't cares for the unused count transitions, and use the standard design procedure, outlined be- low. Perform an analysis (reverse engineering) of your design and draw the resulting State Graph