Question: Design a 4 - bit register with 2 control inputs s 1 and s 0 , 4 data inputs I 3 , I 2 ,
Design a bit register with control inputs s and s data inputs I I I and I and data outputs Q Q Q and Q When ss the register maintains its value. When ss the register loads I I When ss the register clears itself to When ss the register complements itself, so for example would become and would become Problem #: pts Repeat Problem # but when ss the register reverses its bits, so would become and would become
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