Question: Design a 4-bit Parallel-In Serial-Out Shift Left Register using JK Flip flop, such that: a) if the control signal is 1 then parallel load operation

Design a 4-bit Parallel-In Serial-Out Shift Left Register using JK Flip flop, such that: a) if the control signal is 1 then parallel load operation is performed and b) if control signal is 0 then shift operation is performed such that after 4 shifts the content of the register is zero.

It should be a Shift left PISO register and after 4 shifts it's content should be zero. Anyone?

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