$2\mathrm{.}4$ Design a $4-$bit parallel$-$in parallel$-$out $($PIPO$)$ right$-$shift register with D flip$-$flops and the

following inputs$/$outputs and operation:

Parallel$-$out state variables: $Q_3{Q}_2{Q}_1{Q}_0$

Parallel$-$in data: $D_3{D}_2{D}_1{D}_0$

Serial$-$in data: $SI$

Rising$-$edge$-$triggered clock signal: $CLK$

Two control inputs: $S$ and $L$

When $S=L=0$:$,$ hold the states

When $S=0$ and $L=1$ : load the parallel$-$in data

When $S=1$:$,$ right shift the data stored in the register

a$.$ Construct the desired state table for this register.

b$.$ Derive the characteristic equations for the flip$-$flops.

c$.$ Draw the register using four D flip$-$flops with Clock Enable $($CE$)$ inputs, four $2-$to$-1$

MUXes, and one single OR gate. Do not use any other sequential or combinational

devices.