Design a circuit for converting a $16-$bit binary number to BCD$.$ Hint: Look at the $7-$Segment

design exercise for Basys$3$ FPGA.

$2-$ Write the Boolean equations for generate and propagate terms for a $6-$bit carry look$-$ahead

adder.

$3-$ Draw circuit for a parallel multiplier with $3-$bit inputs.

$4-$ Implement a shift$-$and$-$add multiplier with $3-$bit inputs. Show the contents of the

accumulator register for the three cycles when the multiplicand is $101$ and the multiplier is

$110.$

$5-$ Implement the following FIR flters using as few logic resources as possible.

a$.$ G$($z$)=0\mathrm{.}75+0\mathrm{.}125$ z

$-1$

$+0\mathrm{.}6$ z

$-2$

b$.$ G$($z$)=0\mathrm{.}875+0\mathrm{.}325$ z

$-1$

$+0\mathrm{.}46$ z

$-2$

$6-$ Consider the following Verilog code. What would be the frequency of the output clock

$$clk$\_$out$?$

module clock$\_$divider $($

input wire clk$\_$in$,//100$ MHz input clock

input wire reset, $//$ Reset signal

output reg clk$\_$out $//$ output clock

$)$;

parameter DIVISOR $=3571429$;

reg $[31$:$0]$ counter; $//32-$bit counter to handle the division

always @$($posedge clk$\_$in or posedge reset$)$ begin

if $($reset$)$ begin

counter $<=32\text{'}$b$0$; $//$ Reset the counter

clk$\_$out $<=1\text{'}$b$0$; $//$ Reset the output clock

end else begin

if $($counter $==($DIVISOR $-1))$ begin

counter $<=32\text{'}$b$0$; $//$ Reset the counter

clk$\_$out $<=$ ~clk$\_$out; $//$ Toggle the output clock

end else begin

counter $<=$ counter $+1$; $//$ Increment the counter

end

end

end

endmodule