Design a circuit that has two inputs, clk and X, and produces one output O. X may change every Design a circuit that has two inpts,clk and and produces one output O. X may change every clock cycle and the change happens at the falling edge. The circuit samples the input at every rising edge of the clock. O is 1 (for one clock cycle, from positive edge to positive edge) if the last values of X over the last three cycles were 101 (a) Complete the following the state transition diagram for this circuit. Assume that SO is the starting state. Label each arc as X=1 or X=0 to indicate if the change of state occurs when X is 1 or 0, respectively. Within each state write O-1 or O-0 to indicate the output. (20 points) SO S1 S3 S2