Design a clocked synchronous finite state machine with one input A$,$ and

one output X$.$ The output is asserted $($for one clock cycle$)$ whenever the

input sequence $($serial data$)..\mathrm{.}0101...$ has been observed, as long as the

sequence $..\mathrm{.}1100...$ has never been observed.

A typical sample of the input data A and output $x$ are given below $($note

the position of $x=1$ assertions$)$:

A: $01010001010110101011011000101010110000$dots

X: $00001000001000000100000000000000000000$dots

$($a$)$ Draw the state diagram with minimum number of states.

$(9$ marks$)$

$($b$)$ Design and implement the synchronous finite state machine by using

D$-$type flip$-$flops and logic gates of your choice.