Question: Design a CMOS static gate to compute F = ( A + B ) * ( C + D ) with least delay. ( No

Design a CMOS static gate to compute F=(A+B)*(C+D) with least delay. (No additional Boolean
simplification needed). Each input can present a maximum input capacitance of 10C_(inv). The output must drive a
load of 160*C_(inv). C_(inv) denotes the input capacitance of the smallest (2)/(1) inverter. Choose transistor sizes to
achieve least delay.
Design a CMOS static gate to compute F = ( A + B

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